Fast Identification of Error-Prone Patterns for LDPC Codes under Message Passing Decoding

Although density evolution accurately predicts the asymptotic performance of LDPC codes, it provides limited information for codes of short or moderate block length. For this reason, combinatorial methods have been employed to analyze the performance of finite-length LDPC codes under message passing decoding. The error floor phenomenon is a key issue of finite-length effects, which is caused largely by poorly connected subgraphs residing in the LPDC codes structure. Because of the unequal noise immunity of different bit levels, error floors become more pronounced for LDPC-coded high-order modulation. Nevertheless, the enumeration of error-prone patterns that lead to error floors has been proven to be NP-hard, which motivates us to find substitute metrics with manageable complexity. Considering trapping sets always comprise loops of low extrinsic message degree (EMD) and the connectivity of a loop with the residual graph can be characterized by its approximate EMD (ACE), in this paper we propose a fast method to identify loops with low ACE for a given code. In light of this, the vulnerable variable nodes residing on low-ACE loops are judiciously mapped to bit levels benefitting from stronger error protection. As a result, the error floor can be significantly improved at the cost of a minor increase of hardware complexity.