Title :
Mining performance data from sampled event traces
Author :
Portillo, Ricardo ; Villa, Diana ; Teller, Patricia J.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., El Paso, TX, USA
Abstract :
The prominent role of the memory hierarchy as one of the major bottlenecks in achieving good program performance has motivated the search for ways of capturing the memory performance of an application/machine pair that is both practical in terms of time and space, yet detailed enough to gain useful and relevant information. The strategy that we endorse periodically samples events during program execution, producing an event trace that is both manageable and informative. As demonstrated, adopting this strategy, a diverse set of performance issues can be studied using the same set of traces. For example, using one set of traces and our performance evaluation framework, memory access performance, process migration, compulsory and conflict misses, and false sharing can be characterized.
Keywords :
data mining; memory architecture; performance evaluation; random-access storage; sampling methods; storage management; application/machine pair; compulsory misses; conflict misses; false sharing; memory access performance; memory architecture; memory hierarchy; memory performance data mining; performance evaluation framework; process migration; program execution; random access memory; sampled event traces; Analytical models; Counting circuits; Data analysis; Data mining; Discrete event simulation; Hardware; Information analysis; Monitoring; Performance analysis; Telecommunication computing;
Conference_Titel :
Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings. The IEEE Computer Society's 12th Annual International Symposium on
Print_ISBN :
0-7695-2251-3
DOI :
10.1109/MASCOT.2004.1348304