IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements

Author

Kyo, S. ; Koga, T. ; Okazaki, S.

Author_Institution

Comput. & Commun. Media Res., NEC Corp., Kawasaki, Japan

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

294

Abstract

IMAP-CE is the fourth generation of a series of SIMD linear processor arrays based on the IMAP (integrated memory array processor) architecture. The aim of IMAP-CE is to provide a compact, cost effective and yet high performance solution for various embedded real-time vision applications, especially for vision based driving assistance applications in the ITS (intelligent transportation system) fields. IMAP-CE integrates 128 VLIW processing elements, and a RISC control processor which provides the single instruction stream for the processor array. The peak performance of IMAP-CE is up to 51.2 GOPS operating under 100 MHz. This paper describes the design features of IMAP-CE, its enhanced instruction set for image processing, and the estimated performance

Keywords

automated highways; computer vision; embedded systems; parallel architectures; performance evaluation; reduced instruction set computing; traffic engineering computing; video signal processing; 100 MHz; IMAP architecture; IMAP-CE; ITS; RISC control processor; SIMD; VLIW processing elements; embedded real-time vision; enhanced instruction set; image processing; instruction stream; integrated memory array processor; intelligent transportation system; linear processor array; performance; vision based driving asistance; Computer architecture; Costs; Hardware; Intelligent systems; Memory architecture; National electric code; Process control; Reduced instruction set computing; VLIW; Vehicle detection;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 2001. Proceedings. 2001 International Conference on

Conference_Location

Thessaloniki

Print_ISBN

0-7803-6725-1

Type

conf

DOI

10.1109/ICIP.2001.958109

Filename

958109