PVT-aware leakage reduction for on-die caches with improved read stability

A run-time leakage reduction technique for SRAM caches considers architecture and behavior to achieve an optimal tradeoff between overhead energy and leakage savings. A 16kB SRAM shows a 94.2% cell leakage reduction with a 2% performance penalty. Fabricated in a 0.18 μm 6M CMOS process, the 3.2mm×2.9mm die also shows 25% improvement in read stability.