A 4.9mW 270MHz CMOS frequency synthesizer/FSK modulator

Author

Choi, Hyokjae ; Shin, Sangho ; Ku, Yeonwoo ; Jeong, Mooil ; Lee, Kwyro

Author_Institution

Dept. of EECS, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

fYear

2003

Firstpage

443

Lastpage

446

Abstract

A 270 MHz frequency synthesizer/FSK modulator for low-rate WPAN is implemented. It consumes only 4.9 mW, adopting a current re-use technique, self-DC biasing scheme, and appropriate divider architecture. The 3^rd-order feedback type DSM and the high performance charge pump are designed for wide loop bandwidth, which enables the design of a low power and low noise frequency synthesizer. The implemented prototype offers 500 kHz-loop bandwidth and -104dBc/Hz in-band noise. It also plays a role as an FSK modulator which shows only 1.1 dB degradation at 10^-3 symbol BER compared with the ideal FSK-modulator.

Keywords

CMOS integrated circuits; VHF circuits; delta-sigma modulation; error statistics; frequency dividers; frequency shift keying; frequency synthesizers; integrated circuit design; integrated circuit measurement; integrated circuit noise; low-power electronics; modulators; phase noise; radio access networks; 270 MHz; 4.9 mW; 500 kHz; CMOS frequency synthesizers; FSK modulators; charge pumps; current re-use techniques; delta-sigma modulators; frequency dividers; in-band noise; loop bandwidth; low power/low noise frequency synthesizers; low-rate WPAN; phase noise; self-DC biasing schemes; symbol BER; third-order feedback type DSM; wireless personal area network systems; Bandwidth; CMOS logic circuits; Charge pumps; Energy consumption; Frequency conversion; Frequency shift keying; Frequency synthesizers; Phase locked loops; Prototypes; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-7694-3

Type

conf

DOI

10.1109/RFIC.2003.1213981

Filename

1213981