Title :
A pipelined memory-efficient architecture for face detection and tracking on a multicore environment
Author :
Sudha, N. ; Chandrahas, D. Bharat
Author_Institution :
XMOS Semicond. India Pvt. Ltd., Chennai, India
Abstract :
In this extended abstract, we propose a pipelined parallel architecture for face detection that is appropriate for implementation on a multicore environment. The architecture comprises of modules for video frame acquisition, skin pixel detection, binarization, morphological operations and connected component analysis operating in sequence on an image frame. Successive lines of a frame are processed in a pipeline on multicores. Embedded system realization on a multicore XMOS microcontroller runs the drivers for interfacing image sensor and LCD on different cores along with the various stages of the image processing pipeline. The realization achieves a frame rate of 8 frames/second for an image size of 480×272. Further, the solution is area-efficient and is based on a single XMOS sliceKIT with support for camera, LCD and other units.
Keywords :
embedded systems; microcontrollers; multiprocessing systems; object detection; object tracking; parallel architectures; video signal processing; XMOS sliceKIT; binarization; connected component analysis; embedded system; face detection; face tracking; image frame sequence; morphological operations; multicore XMOS microcontroller; multicore environment; pipelined memory-efficient architecture; pipelined parallel architecture; skin pixel detection; video frame acquisition; Face; Face detection; Multicore processing; Pipelines; Skin; Streaming media;
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208145