An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code

In this paper, we discuss the design and testing results of an analog 0.35 μm CMOS turbo decoder for the rate-1/3, 40 bit UMTS turbo code. The prototype was successfully tested at nominal conditions (2 Mbit/s), with an overall power consumption of 10.3 mW at 3.3 V. The tested BER curve shows a limited performance loss (about 0.5 dB) with respect to that of the digital implementation. We also discuss a discrete-time model of the analog decoder which allows us to run BER simulations including circuit transient behavior and device mismatch in a very short time. Circuit-level simulations demonstrate the validity of our model. According to the discrete-time simulation, a significant contribution to the performance loss is due to device mismatch.