Low frequency dithering technique for linearization of voltage mode class-D amplifiers

Author

Malekzadeh, F.A. ; Mahmoudi, R. ; van Roermund, Arthur

Author_Institution

Electr. Eng. Dept., Univ. of Waterloo, Waterloo, ON, Canada

fYear

2013

Firstpage

91

Lastpage

93

Abstract

This paper introduces a novel technique for simultaneous linearity and efficiency enhancement of class-D amplifiers by combining a low frequency sinusoid, known as dither, with a bandpass signal. The proposed technique improves the linearity due to dither averaging effect, and power efficiency, due to the reduction of reactive loss. The feasibility of the idea is verified through realization and measurement of a 65nm TSMC CMOS voltage mode class-D amplifier operating at 1 GHz. The drain efficiency is enhanced from 19.2 to 37 percent, while providing ACPR of -33dBc for the first adjacent WCDMA channel.

Keywords

CMOS analogue integrated circuits; amplifiers; code division multiple access; ACPR; TSMC CMOS voltage mode class-D amplifier; bandpass signal; first adjacent WCDMA channel; frequency 1 GHz; low frequency dithering technique; low frequency sinusoid; power efficiency; size 65 nm; voltage mode class-D amplifier linearization; Band-pass filters; CMOS integrated circuits; Frequency measurement; Linearity; Multiaccess communication; Pulse width modulation; Voltage measurement; PAPR; Power amplifiers; class-D; dither; efficiency; linearity; load pull measurements;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Symposium (RWS), 2013 IEEE

Conference_Location

Austin, TX

ISSN

2164-2958

Print_ISBN

978-1-4673-2929-3

Electronic_ISBN

2164-2958

Type

conf

DOI

10.1109/RWS.2013.6486651

Filename

6486651