Title :
High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems
Author :
Sun, Yang ; Karkooti, Marjan ; Cavallaro, Joseph R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX
Abstract :
This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is described
Keywords :
IEEE standards; OFDM modulation; application specific integrated circuits; decoding; encoding; field programmable gate arrays; ASIC resource requirements; FPGA; IEEE 802.11n standard; architecture-aware LDPC codes; block lengths; code rates; high throughput parallel scalable LPDC encoder/decoder architecture; irregular LDPC coding; joint LDPC coding-decoding hardware architecture; wireless OFDM systems; Application specific integrated circuits; Code standards; Decoding; Field programmable gate arrays; Hardware; OFDM; Parity check codes; Prototypes; Testing; Throughput;
Conference_Titel :
Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on
Conference_Location :
Richardson, TX
Print_ISBN :
1-4244-0670-6
Electronic_ISBN :
1-4244-0670-6
DOI :
10.1109/DCAS.2006.321028
