Title :
500 MHz testing on a 100 MHz tester
Author :
Wimmers, Didier ; Sakaitani, Kris ; West, Burnell
Author_Institution :
Schlumberger Technol., San Jose, CA, USA
Abstract :
This paper describes an innovative way to test certain classes of complex digital devices at speeds of 500 MHz or more in a 100 MHz tester whose architecture incorporates the ability to generate a large number of edges per tester period. The means for generating the test patterns, and the means for executing them, are both described
Keywords :
automatic test equipment; automatic testing; computer architecture; electronic equipment testing; logic testing; multichip modules; 100 MHz; 500 MHz; ATE; architecture; clock generation; complex digital devices; drive control formatter; edges; high speed gate array; load board design; logic IC; multichip module testing; performance testing; response control formatter; response evaluation; test pattern generation; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit testing; Clocks; Costs; High speed integrated circuits; Logic testing; System testing; Timing;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527959
