Title :
Precise timing verification of logic circuits under combined delay model
Author :
Kimura, S. ; Kashima, S. ; Haneda, H.
Author_Institution :
Dept. of Electron. Eng., Kobe Univ., Japan
Abstract :
A combined delay model to manipulate the variance of the delay time of logic elements and a timing verification method based on the theory of regular expressions are presented. Emphasis is placed on the hazard detection problem and the verification of asynchronous circuits. The effectiveness of the method with medium sized circuits including about 100 elements is shown.<>
Keywords :
clocks; delay circuits; logic CAD; logic circuits; asynchronous circuits; combined delay model; delay time; hazard detection problem; logic circuits; logic elements; timing verification method; Clocks; Delay circuits; Design automation; Logic circuits;
Conference_Titel :
Computer-Aided Design, 1992. ICCAD-92. Digest of Technical Papers., 1992 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-3010-8
DOI :
10.1109/ICCAD.1992.279317
