Timing distribution in VHDL behavioral models

A CAD tool, TIMESPEC, developed for solving the timing distribution problem of allocating realistic delays to the internal primitives (RTL models) of a digital device by using the linear programming approach is described. The inconsistencies in the manufacturer´s specifications are also detected and corrected. TIMESPEC allows the use of embedded timing in behavioral VHDL models, and thus the end-to-end delays for all paths in the digital device are made available. An interface is provided with an X Windows based graphical tool, the Modeler´s Assistant, which allows enumeration of all the input-to-output paths in the device. Thus a CAD tool is made available to system or chip designers/modelers for building accurate and synthesizable VHDL models.<>