DC bus electrolytic capacitor stress in adjustable- speed drives under input voltage unbalance and sag conditions

This work analyzes the effects of the input voltage unbalance and sags on the DC bus electrolytic capacitors in adjustable-speed drives (ASDs) in order to predict their impact on expected capacitor lifetime. The key phenomenon that causes these problems is the transition of the rectifier stage from three-phase to single-phase operation. Since the ESR (equivalent series resistance) increases at low frequencies, the low-order harmonic current components (120 Hz, 240 Hz, etc.) contribute disproportionately to the capacitor power losses and temperature rise, resulting in reduced lifetime. Closed-form expressions are developed for predicting these effects including the impact of finite line impedance, finite bus capacitance, and varying load. The impact of inverter SVPWM (space vector pulse width modulation) switching on the capacitor loss is also included. Simulations and experimental tests are used to verify the accuracy and effectiveness of the closed-form analysis using a 5 hp ASD system.