Title :
Optimization of capacitive divider for 8-bit DAC realized in 65 nm CMOS process
Author :
Jaworski, Zbigniew
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
Capacitor based DACs are common designer´s choice for projects realized in nanometer technologies. Designs kits provide several devices that can be used as capacitors. However, they exhibit serious differences in terms of linearity, minimum area and sensitivity to process disturbances The paper presents analysis of capacitive divider design to be used in 8-bit DAC realized in 65 nm CMOS process. Various devices utilized as capacitor are examined in order to select the most suitable one for the DAC implementation in respect to resolution, conversion time and layout area.
Keywords :
CMOS integrated circuits; circuit optimisation; digital-analogue conversion; integrated circuit layout; voltage dividers; CMOS process; DAC resolution; capacitive divider optimization; conversion time; digital-analog converter; layout area; size 65 nm; Capacitance; Capacitors; Layout; Linearity; Sensitivity; Switches; Transistors; CMOS; DAC; capacitor; divider; nanometer technology; process disturbances;
Conference_Titel :
Mixed Design of Integrated Circuits & Systems (MIXDES), 2015 22nd International Conference
Conference_Location :
Torun
Print_ISBN :
978-8-3635-7806-0
DOI :
10.1109/MIXDES.2015.7208544
