Novel level-up shifters for high performance and low power mobile devices

This paper presents novel level-up shifters called Dual Step Level-up Shifter (DSLS) and Stacked Dual Step Level-up Shifter (SDSLS) which are simpler, yet more efficient than conventional level-up shifters. We compare the proposed designs with two existing designs: a conventional level-up shifter and Contention-Mitigated Level Shifter (CMLS). The delay of the proposed designs is less than that of a conventional level-up shifter and CMLS by up to 4.86% and 6.51%, respectively. The power consumption of the proposed designs is less than that of a conventional level-up shifter and CMLS by up to 6.68% and 5.40%, respectively. DSLS and SDSLS act as a power gating circuit as well as a level-up shifter. Thus, we conclude that our proposed designs are very effective for low power designs.