Title :
Model Order Reduction with Load Constraints
Author :
Ma, Min ; Khazaka, Roni
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que.
Abstract :
This paper presents an efficient model order reduction method which can be used for interconnect networks with a large number of ports. The proposed method significantly reduces the size of the macromodel by incorporating practical constraints on the types of loads that can be connected at the output ports
Keywords :
integrated circuit interconnections; integrated circuit modelling; interconnect networks; load constraints; macromodel; model order reduction; output ports; Admittance; Electronics packaging; Equations; Integrated circuit interconnections; Load modeling; Resistors; Telephony; Transmission line matrix methods; Transmission lines; Voltage;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2006 IEEE
Conference_Location :
Scottsdale, AZ
Print_ISBN :
1-4244-0668-4
DOI :
10.1109/EPEP.2006.321226
