Design of modified low power booth multiplier

The design of normal multiplier consumes most of the power in DSP processors. In order to reduce the power consumption of multiplier, the low power Booth recoding methodology is implemented by recoding technique. This booth decoder will increase number of zeros in multiplicand. Booth multiplier has booth decoder to recode the given input to booth equivalent. Hence the number of switching activity will be reduced so the power consumption of the design can be reduced. The input bit coefficient will determine the switching activity of the component that is when the input coefficient is zero corresponding rows or column of the adder should be deactivated. When multiplicand contains more number of zeros the higher power reduction can takes place. So in booth multiplier high power reductions will be achieved.