Title :
Automatic failure analysis system for high density DRAM
Author :
OH, Sang-Chul ; Kim, Jae-Ho ; Choi, Ho-Jeong ; Choi, Si-Don ; Park, Ki-Tae ; Park, Jong-Woo ; Lee, Wha-Joon
Author_Institution :
Memory Bus. Div., Samsung Electronics Co., Suwon, South Korea
Abstract :
In this paper, the automatic failure analysis method based on the random bit failure causing the major yield drop in DRAM and the analysis system named “SEC FAILURE ANALYSIS SYSTEM” are discussed. This system is developed for the accurate and rapid electrical analysis of the failure in a statistical manner in order to make a quick feedback to the manufacturing process
Keywords :
DRAM chips; automatic testing; failure analysis; fault diagnosis; statistical analysis; automatic failure analysis; electrical analysis; feedback; high density DRAM; random bit failure; test vector generation; yield drop; Automatic testing; Dielectric materials; Dielectric substrates; Failure analysis; Feedback; Manufacturing processes; Material storage; Random access memory; Subthreshold current; System testing;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.527995
