MINoC: Providing configurable high throughput interconnection for MPSoCs

In a near future scenario, Multi-Processors System-on-Chip (MPSoCs) designs will require very flexible interconnections, able to support different and heterogeneous applications, thus allowing bandwidth changes and power optimizations in the same application. In this paper we propose the MINoC (Multi-Interconnections Network-on-Chip) architecture that allows three switching possibilities: packet switching, buffered circuit switching and unbuffered circuit switching. Besides providing this adaptability, we show use cases for each of the possible switching activities. Thus, with this proposal, one can obtain up to 88% of reduction in the average latency and an improvement of up to 7.9 times the average throughput over standard packet switching for the benchmarks considered in these analyses.