Improving testability and fault analysis in low level design

In earlier, Fault Analysis (FA) has been exploited for several aspects of analog and digital testing. These include, test development, Design for Test (DFT) schemes qualification, and fault grading. Higher quality fault analysis will reduce the number of defective chips that slip past the tests and end up in customer´s systems. This is commonly referred to as defective parts per million (DPM) that are shipped. This paper attempts to improve the fault diagnosis, controllability and testability of testing methodology. The proposed test method takes the advantage of good fault coverage in low level designs. In this low level design, I_DDQ fault was focused and the testability has been enhanced in the testing procedure using a simple fault injection technique. The faults have been diagnosed by building a Built-in Current Sensor (BISC). Here the design under test (DDT) is two-stage CMOS Operational amplifier. The simulated result confirms that the number of patterns used for testing is reduced and the test coverage is also increased.