CD-SEM metrology evaluation of gate-all-around Si nanowire MOSFET with improved control of nanowire suspension by using a buried boron nitride etch-stop layer

Author

Cohen, Guy M. ; Shi, Li-Hua ; Bangsaruntip, Sarunya ; Grill, A. ; Neumayer, Deborah ; Levi, Shimon ; Weinberg, Yakov ; Shoval, Ori ; Adan, Ofer ; Tzi, Maayan Bar ; Conley, Amiad

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2014

fDate

19-21 May 2014

Firstpage

248

Lastpage

251

Abstract

In this work, we report a new fabrication method of Si nanowires that enables an accurate control of the suspension gap underneath the Si wire. It is achieved by using SOI wafers with an embedded boron nitride (BN) etch-stop layer. Physical characterization of the Si wires was performed with a 3D-CDSEM, measurement results are compared with the process of record where conventional SOI wafers are used. Metrology measurements provide new insights on the effect of SEM induced charge in altering the buckling orientation of imaged Si wires.

Keywords

MOSFET; elemental semiconductors; nanowires; scanning electron microscopy; silicon; silicon-on-insulator; 3D-CDSEM; SEM induced charge; SOI wafers; Si; buckling orientation; embedded boron nitride etch-stop layer; gate-all-around Si nanowire MOSFET; imaged Si wires; metrology measurements; nanowire suspension; suspension gap; Films; Logic gates; Rough surfaces; Silicon; Surface treatment; Suspensions; Wires; 3D-CDSEM; Boron Nitride; Gate-all-around (GAA) nanowire MOSFETs SOI;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI

Conference_Location

Saratoga Springs, NY

Type

conf

DOI

10.1109/ASMC.2014.6847014

Filename

6847014