Title :
Reduced scan shift: a new testing method for sequential circuits
Author :
Higami, Yoshinobu ; Kajihara, Seiji ; Kinoshita, Kozo
Author_Institution :
Fac. of Eng., Osaka Univ., Japan
Abstract :
This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences. In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible. For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors. Experimental results for ISCAS´89 benchmark circuits are given to show the effectiveness of this method
Keywords :
fault diagnosis; flip-flops; integrated logic circuits; logic testing; performance evaluation; sequential circuits; ISCAS´89 benchmark circuits; LSI; flip-flops; order of test vectors; reduced scan shift; scan chain; scan input line; scan shift operations; sequential circuits; short test sequences; target faults; Benchmark testing; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Flip-flops; Large scale integration; Sequential analysis; Sequential circuits;
Conference_Titel :
Test Conference, 1994. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2103-0
DOI :
10.1109/TEST.1994.528007
