Title :
A new efficient design of the 2-to-1 multiplexer
Author :
Kayed, Somia I. ; Ragaie, Hani F.
Author_Institution :
Nuclear Mater. Authority, Cairo, Egypt
Abstract :
By using the differential pass-transistor logic technique (DPTL), a 2-to-1 selector is designed in 2 μm technology. This logic technique offers greater area efficiency, higher speed of operation, and simpler design algorithms than conventional techniques. A DPTL buffer is also proposed. DPTL buffers are able to generate standard CMOS levels regardless of input signal-swing variation while providing noise immunity by maintaining the structural symmetry. Circuit structures are presented and are compared with the conventional NMOS pass transistor and CMOS transmission gate
Keywords :
CMOS logic circuits; buffer circuits; logic design; multiplexing equipment; 2 micron; 2-to-1 multiplexer; DPTL buffers; area efficiency; differential pass-transistor logic; noise immunity; standard CMOS levels; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Circuit noise; Logic design; MOS devices; Multiplexing; Noise generators; Noise level; Signal generators;
Conference_Titel :
Microelectronics, 1995. Proceedings., 1995 20th International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-2786-1
DOI :
10.1109/ICMEL.1995.500974
