Efficient simulation of chip-to-chip interconnect system by combining waveform relaxation with reduced-order modeling methods

A new method is proposed for an efficient transient analysis of an interconnect-dominated system with a large number of linear, lumped and distributed elements and few nonlinear driver and termination networks. The method is based on partitioning the system into linear and nonlinear subnetworks and solving each subsystem iteratively using waveform relaxation technique. This allows a suitable and efficient simulation technique to be applied on each subnetwork. The linear network is analyzed using a reduced-order-modeling technique in the frequency domain and the time-domain waveforms are obtained using the inverse Laplace transform relation and reclusive convolution in the absence of the nonlinear networks. The method improves the simulation speed and accuracy because smaller nonlinear circuits are solved using conventional simulation methods. The technique and the validity of the method are discussed with an example using the Rambus memory channel.