Title :
Yield prediction using calibrated critical area modelling
Author :
Gaston, G.J. ; Allan, G.A.
Author_Institution :
GEC Plessey Semicond., Plymouth, UK
Abstract :
This paper describes how critical area software can be used in the accurate prediction of the yield of ASIC designs. The approach is based on calculating the actual area of the design most sensitive to defects, rather than using the traditional methods of using die area to calculate the yield. An obstacle course test structure is used to calibrate the software tools, by extracting values for inter and intra layer defect densities. The tools are then used to predict yield improvements on designs which have been modified to improve process yield
Keywords :
SRAM chips; application specific integrated circuits; calibration; integrated circuit design; integrated circuit modelling; integrated circuit yield; ASIC designs; calibrated critical area modelling; interlayer defect densities; intralayer defect densities; obstacle course test structure; process yield; yield prediction; Application specific integrated circuits; Circuit faults; Circuit testing; Data mining; Electronics industry; Integrated circuit yield; Predictive models; Random access memory; Semiconductor device manufacture; Software testing;
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
DOI :
10.1109/ICMTS.1997.589292
