An analog CMOS Viterbi detector for digital magnetic recording

Author

Matthews, T.W. ; Spencer, R.R.

Author_Institution

California Univ., Davis, CA, USA

fYear

1993

Firstpage

214

Lastpage

215

Abstract

A fully-integrated analog Viterbi detector is presented. Four chips, each containing two VA (Viterbi algorithm) dicode detectors, have been fabricated in the standard 2- mu m, double-poly, p-well MOSIS CMOS process. By externally interleaving the two-dicode outputs, each part operates at over 40 Mb/s on a PR class IV (PR4) channel. The chip consumes under 100 mW from a single 5-V supply. The active area is 1.8 mm*1.8 mm (2.2 mm*2.2 mm with pads). Two main functions are implemented by the Viterbi detector: (1) metric calculation and (2) survivor sequence storage (path memory). The path memory is straightforward, digital, and is designed using true single-phase clocked flip-flops.<>

Keywords

CMOS integrated circuits; detector circuits; mixed analogue-digital integrated circuits; 100 mW; 2 micron; 40 Mbit/s; 5 V; PR class IV channel; active area; analog CMOS Viterbi detector; digital magnetic recording; double-poly process; metric calculation; p-well MOSIS CMOS process; path memory; single-phase clocked flip-flops; survivor sequence storage; two-dicode outputs; Clocks; Detectors; Digital magnetic recording; Equations; Master-slave; Maximum likelihood estimation; Switches; Timing; Viterbi algorithm; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1993. Digest of Technical Papers. 40th ISSCC., 1993 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0987-1

Type

conf

DOI

10.1109/ISSCC.1993.280043

Filename

280043