H.263 mobile video codec based on a low power consumption digital signal processor

Author

Naito, Yukihiro ; Kuroda, Ichiro

Author_Institution

C&C Media Res. Labs., NEC Corp., Kawasaki, Japan

Volume

5

fYear

1998

Firstpage

3041

Abstract

This paper describes an H.263 video codec implementation based on a low power consumption general purpose DSP. Fast algorithms, such as a fast motion estimation algorithm and a low complexity noise reduction filter, are proposed to implement the video codec on a single DSP chip maintaining sufficient picture quality. By using a 50 MIPS, 100 mW DSP, the developed codec encodes and decodes 7.5 QCIF frames per second, which is sufficient performance for low bit-rate video compression, typically below 64 kbps

Keywords

computational complexity; data compression; digital signal processing chips; interference suppression; land mobile radio; motion estimation; radio equipment; video codecs; 100 mW; 50 MIPS; 64 Mbit/s; DSP; H.263 mobile video codec; fast motion estimation algorithm; low bit-rate video compression; low complexity noise reduction filter; low power consumption digital signal processor; picture quality; Digital signal processing; Digital signal processing chips; Digital signal processors; Energy consumption; Filters; Motion estimation; Noise reduction; Signal processing algorithms; Video codecs; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on

Conference_Location

Seattle, WA

ISSN

1520-6149

Print_ISBN

0-7803-4428-6

Type

conf

DOI

10.1109/ICASSP.1998.678167

Filename

678167