• DocumentCode
    1697697
  • Title

    Performance of Switch Blocking on Multithreaded Architectures

  • Author

    Gopinath, Krishnasamy ; M.k., Krishna ; Lim, B.H. ; Agarwal, Abhishek

  • Author_Institution
    Indian Institute of Science, India
  • Volume
    1
  • fYear
    1994
  • Firstpage
    275
  • Lastpage
    284
  • Abstract
    Block multithreaded architectures tolerate large memory and synchronization latencies by switching contexts on every remote-memory-access or on a failed synchronization request. We study the performance of a waiting mechanism called switch-blocking where waiting threads are disabled (but not unloaded) and signalled at the completion of the wait in comparison with switch-spinning where waiting threads poll and execute in a round-robin fashion. We present an implementation of switch-blocking on a simulator for Alewife (a block multithreaded machine) for both remote memory accesses and synchronization operations and discuss results from the simulator. Our results indicate that switch-blocking has the same problems that switch-spinning has under heavy lock contention and that support for switch-blocking for remote memory accesses may not be judicious at current range of memory access times but may be so in the future due to its strong interactions with synchronization operations.
  • Keywords
    Decoding; Digital signal processors; Dynamic scheduling; Microprocessors; Out of order; Parallel processing; Runtime; Switches; VLIW; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing, 1994. Vol. 1. ICPP 1994. International Conference on
  • Conference_Location
    North Carolina State University, NC, USA
  • ISSN
    0190-3918
  • Print_ISBN
    0-8493-2493-9
  • Type

    conf

  • DOI
    10.1109/ICPP.1994.161
  • Filename
    4115731