Optimizing boundary scan in a proprietary environment

Boundary scan provides test engineers with a powerful tool for detecting both board-level and chip-level faults. The benefits of boundary scan can be diminished, however, when commonly used design and test generation tools are tied to a specific implementation (standard) of boundary scan. By requiring a specific implementation, test tools may limit a designer´s ability to design an optimal product. A “higher” level standard is required which abstracts the concept of accessibility to device I/O from specific implementation details. Abstracting information required for tool developers from implementation details should allow tools to become more flexible, enabling designers to optimize their specific boundary scan implementation without losing the benefit of the tools themselves