Filling the via hole of IC by VPES (Vacuum Printing Encapsulation Systems) for stacked chip (3D packaging)

The most important process for the development of 3-dimensional packaging, especially wafer stacking, is studied in this paper. This is the process of via hole filling; via holes require filling with conductive paste for connection or non-conductive paste for reliability. VPES (Vacuum Printing Encapsulation System) is useful for the process of filling the paste in small via holes. This process is also suitable for filling via holes of a functional substrate and glass. Various types of paste (both of conductive paste and nonconductive paste) were studied to aid the selection of paste for the requirement of packaging. It was most difficult and important that printing conditions (printing times, vacuum condition etc.) were different for each paste. Printing conditions for each paste were confirmed and the mechanisms for filling of via hole by VPES were identified. The printing condition depends on the structure of via hole (design, aspect ratio, diameter and depth etc.), also the properties of the filling paste (viscosity and thixotropic index etc.).