DocumentCode
1698548
Title
Low-power fixed-width array multipliers
Author
Wang, Jinn-Shyan ; Kuo, Chien-Nan ; Yang, Tsung-Han
Author_Institution
Inst. of Electr. Eng., Chung-Cheng Univ., Chia-Yi, Taiwan
fYear
2004
Firstpage
307
Lastpage
312
Abstract
A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8% speed improvement but also gains 14% power and 13% area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%.
Keywords
high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; multiplying circuits; high-speed design; left-to-right algorithm; low power design; low-power fixed-width array multipliers; multiplier area reduction; multiplier speed; partial-product reduction; power reduction; voltage scaling; Algorithm design and analysis; Arithmetic; Compressors; Digital signal processing chips; Digital signal processors; Kernel; Logic design; Permission; Signal processing algorithms; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on
Print_ISBN
1-58113-929-2
Type
conf
DOI
10.1109/LPE.2004.1349356
Filename
1349356
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