DocumentCode
1699804
Title
A low-power Booth multiplier using novel data partition method
Author
Park, Jongsu ; Kim, San ; Lee, Yong-Surk
Author_Institution
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear
2004
Firstpage
54
Lastpage
57
Abstract
The Booth algorithm has a characteristic that the Booth algorithm produces the Booth encoded products with a value of zero when input data stream have sequentially equal values. Therefore, partial products have greater chances of being zero when the one with a smaller dynamic range of two inputs is used as a multiplier. To minimize greater switching activities of partial products, we propose a novel multiplication algorithm and its associated architecture. The proposed algorithm divides a multiplication expression into four multiplication expressions, and each multiplication is computed independently. Finally, the results of each multiplication are added. Therefore, the exchanging rate of two input data calculations can be higher during multiplication. Implementation results show the proposed multiplier can maximally save about 20% in terms of power dissipation than the previous Booth multiplier.
Keywords
digital arithmetic; digital signal processing chips; multiplying circuits; system-on-chip; Booth algorithm; Booth encoded products; DSP cores; comparator; data partition method; exchanging rate; input data calculations; low-power Booth multiplier; multiplication algorithm; partial products; power dissipation; radix-4 Booth algorithm; Capacitors; Circuits; Data engineering; Digital signal processing; Energy consumption; Equations; Laboratories; Mobile communication; Partitioning algorithms; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-8637-X
Type
conf
DOI
10.1109/APASIC.2004.1349403
Filename
1349403
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