Design of low cost fault tolerant analog circuits using real-time learned error compensation

Analog checksum based fault tolerance for linear circuits has been proposed in the past but remains a theoretical artifact due to the high cost and complexity of error compensation while other redundancy based methods have prohibitive overheads. To resolve this, new low cost error compensation methods for widely used linear analog circuits are developed in this research. Trial and error based compensation learning methods combined with the use of less than minimum distance codes are used for failure tolerance. This results in significant hardware savings over prior correction schemes with minimal increase in error correction latency. It is shown how dual failures in analog circuits, not possible with existing techniques, can be compensated using the proposed fault-learning approach.