A 12-b 56MS/s pipelined ADC in 65nm CMOS

This paper describes a 1.2 V, 12-b pipelined ADC implemented in a 65 nm CMOS process. The circuit design techniques used to obtain high gain operational amplifiers in a deep-submicron process are described. A novel top-level simulation methodology is used to quantify the transient errors in each subrange stage, allowing their optimal design. The circuit employs various techniques for power reduction: class A-B op-amps, improved reference design, and frequency-to-current biasing.