DocumentCode
1703872
Title
Extended Petri nets based hierarchical test generation
Author
Kadim, H.J. ; Taylor, G.E.
Author_Institution
Dept. of Electron. Eng., Hull Univ., UK
fYear
1993
fDate
5/28/1993 12:00:00 AM
Firstpage
42675
Lastpage
42679
Abstract
The work presented has two major aspects which are the modelling of the circuit in a manner suitable for hierarchical implementation, and the introduction of graph theory in the analysis process to point out symmetries and testability related information, which have the effect of minimising time requirements and avoiding unnecessary processing
Keywords
Petri nets; VLSI; automatic testing; integrated circuit testing; logic testing; analysis process; graph theory; hierarchical implementation; hierarchical test generation; modelling; symmetries; testability related information; time requirements;
fLanguage
English
Publisher
iet
Conference_Titel
Testing-the Gordian Knot of VLSI Design, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
280382
Link To Document