DocumentCode :
1704405
Title :
Algorithm and architecture for high speed merged arithmetic FIR filter generation
Author :
Castellano, Marco ; Baldrighi, Paola ; Vacchi, Carla ; Natuzzi, Mauro
Author_Institution :
Dept. of Electron., Univ. of Pavia, Pavia
fYear :
2008
Firstpage :
197
Lastpage :
202
Abstract :
This paper presents a new method and an algorithm for the synthesis of a high-speed variable coefficients Finite Impulse Response (FIR) filter. Timing performance and reduced area are achieved employing two techniques. Firstly, a merged arithmetic architecture is used to synthesize the FIR filter function directly. Secondly, an algorithm that looks for minimum delay Partial Product Reduction Tree (PPRT) is developed. These results are combined to create a program that furnishes a speed optimized netlist for the filter. The performance of the proposed method has been evaluated by comparing it to the result achieved by cell-based synthesis software.
Keywords :
FIR filters; network synthesis; timing; FIR Filter; cell-based synthesis software; high-speed variable coefficients finite impulse response filter; partial product reduction tree; speed optimized netlist; Added delay; Adders; Arithmetic; Counting circuits; Finite impulse response filter; Integrated circuit interconnections; Memory; Partitioning algorithms; Software performance; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Control and Signal Processing, 2008. ISCCSP 2008. 3rd International Symposium on
Conference_Location :
St Julians
Print_ISBN :
978-1-4244-1687-5
Electronic_ISBN :
978-1-4244-1688-2
Type :
conf
DOI :
10.1109/ISCCSP.2008.4537219
Filename :
4537219
Link To Document :
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