A switched-capacitor N-path decimating filter

In this paper we present the first switched-capacitor (SC) circuit implementation of an N-path decimating filter which has the ability to perform downconversion simultaneous with high filtering while enabling the use of operational amplifiers with relaxed specifications when compared with the traditional SC N-path filters. The example given is of a 4-path system using high-pass decimating filters with input and output sampling frequency of 40 MHz and 13.3 MHz, respectively, yielding an overall input sampling frequency of 160 MHz and thus extended input baseband from 0 to 80 MHz. The detailed simulation analysis of the circuit illustrates the resulting frequency downconversion from 60 MHz to 6.6 MHz as well as the effect of various sources of errors, e.g., operational amplifier offset and gain errors, capacitance mismatch and clock skew, in the overall baseband response and image rejection performance