3D placement algorithm with vertical via count constraints

Author

Liu, Guilin ; Li, Zhuoyuan ; Zhou, Qiang ; Xianlong Hong

Author_Institution

Graduate Sch. at Shenzhen, Tsinghua Univ., Beijing, China

Volume

2

fYear

2005

Lastpage

1234

Abstract

Three-dimensional (3D) packaging via system-on-package is a potential alternative to meet the rigorous requirement of the interconnect delay problem. A 3D placement algorithm for two-stacked-die integration is proposed for wire length optimization. Cells are pre-partitioned into different dies to solve the conflict between wire length reduction and vertical via count constraint. A quadratic placement algorithm is adopted to place them on each die. Experimental results on a set of test cases from industry indicate the effectiveness and efficiency of our algorithm.

Keywords

circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; quadratic programming; 3D placement algorithm; interconnect delay problem; quadratic placement algorithm; quadratic programming; system-on-package; three-dimensional packaging; two-stacked-die integration; vertical via count constraints; wire length optimization; wire length reduction; Assembly; Circuit testing; Computer science; Constraint optimization; Delay; Integrated circuit interconnections; Packaging; Partitioning algorithms; Quadratic programming; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on

Print_ISBN

0-7803-9015-6

Type

conf

DOI

10.1109/ICCCAS.2005.1495329

Filename

1495329