An efficient line-based architecture for 2-D discrete wavelet transform

An efficient line-based VLSI architecture for the 9/7 2D discrete wavelet transform (DWT) based on a lifting scheme, is proposed in this paper, which consists of a horizontal filter and a vertical filter working in parallel and pipeline. The embedded decimation technique based on fold and time multiplexing is exploited to optimize the architecture, which reduces significantly the required number of multipliers, adders and registers, as well as the size of buffer memory and the amount of RAM access, and hence decreases efficiently the occupied area of the design. The architecture is designed to generate a subband coefficient per clock cycle, and the four subband coefficients of the transformed signal are available interleaved. The proposed architecture has many advantages including short output latency, simple data flow, better regularity and scalability, etc.