A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range

A pixel clock generator is widely utilized in the analog front-ends of digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it difficult to achieve good jitter performance, because noise from the VCO cannot be sufficiently removed due to the limited loop bandwidth. In this work, a dual-loop architecture is adopted to reduce the phase noise from the VCO based on a ring oscillator. Prior work [1] proposed a dual-loop hybrid PLL composed of an analog loop for the DCO and the digital main loop. Unlike the hybrid architecture [1], our proposed PLL is composed of purely digital components and is synthesized in 28nm CMOS, including the TDC and the DCO, using a cell-based design methodology and automated layout synthesis.