DocumentCode
170676
Title
Auto-parallelization of data structure operations for GPUs
Author
Nasre, Rupesh
Author_Institution
IIT Madras, Chennai, India
fYear
2014
fDate
12-17 Oct. 2014
Firstpage
1
Lastpage
10
Abstract
We present an auto-parallelization technique for generating GPU implementation of data-structure operations from a sequential specification. The technique partitions the data-structure operations into barrier-separated phases such that each phase executes only homogeneous operations. Homogeneity is dictated by the method type, which is derived from the specification. Two key aspects of our technique are: (i) it ensures linearizability of the data-structure, and (ii) it is capable of composing multiple data-structure operations with the guarantee of optimal barrier placement, which we formally prove. We illustrate the usefulness of our techniques by synthesizing efficient GPU implementations of practical graph algorithms like single-source shortest paths which uses a concurrent worklist, Delaunay mesh refinement that uses a worklist and a mesh, and a doubly linked-list supporting arbitrary insertion and deletion.
Keywords
data structures; graphics processing units; parallel processing; Delaunay mesh refinement; GPU; auto-parallelization technique; barrier-separated phase; concurrent worklist; data structure operation; doubly linked-list supporting arbitrary deletion; doubly linked-list supporting arbitrary insertion; graphics processing unit; homogeneous operation; optimal barrier placement; sequential specification; Data structures; Graphics processing units; Instruction sets; Kernel; Libraries; Synchronization; Synthesizers; Auto; GPGPU; data structures; parallelization;
fLanguage
English
Publisher
ieee
Conference_Titel
Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2014 International Conference on
Conference_Location
Jaypee Greens
Type
conf
DOI
10.1145/2656106.2656115
Filename
6972460
Link To Document