DocumentCode
1706844
Title
A 6.3µW 20b incremental zoom-ADC with 6ppm INL and 1µV offset
Author
Youngcheol Chae ; Souri, K. ; Makinwa, Kofi A. A.
Author_Institution
Yonsei Univ., Seoul, South Korea
fYear
2013
Firstpage
276
Lastpage
277
Abstract
Incremental analog-to-digital converters (ADCs) can be applied in many instrumentation applications, such as the readout of bridge transducers and smart sensors [1-4]. Such applications require ADCs with high absolute accuracy and linearity, as well as high resolution. Moreover, since the signals of interest are typically near DC, such ADCs must employ robust offset and 1/f noise-reduction techniques. Fulfilling these requirements often results in ADCs with poor energy efficiency, thus preventing their use in systems powered by batteries or energy scavengers. This paper describes a micro-power incremental ADC that achieves 20b resolution, 1μV offset and 6ppm INL, while dissipating more than an order of magnitude less energy than ADCs with comparable precision [3-6]. This is achieved by the use of a 2-step or zoom ADC architecture [1,2], an inverter-based integrator, and various dynamic error-correction techniques.
Keywords
1/f noise; analogue-digital conversion; energy conservation; error correction; invertors; 1/f noise-reduction technique; ADC architecture; INL; bridge transducer readout; dynamic error-correction technique; energy efficiency; incremental analog-to-digital converter; incremental zoom-ADC; inverter-based integrator; micropower incremental ADC; power 6.3 muW; robust offset; smart sensor; voltage 1 muV; word length 20 bit; 1f noise; Capacitors; Inverters; Linearity; Modulation; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4673-4515-6
Type
conf
DOI
10.1109/ISSCC.2013.6487733
Filename
6487733
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