Investigation of effects of die thinning on central TSV bus driver thermal performance

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of a single TSV bus driver/receiver is impacted by die thinning. Die thinning limits the ability for heat to diffuse into the wafer, however decreasing the capacitance of the TSV can decrease the driver´s power leading to an overall lower working temperature. In this work we found that thinning the top wafer with TSVs from 100 μm to 25 μm allowed for up to a 65% decrease in the steady-state temperature rise of a TSV driver/receiver running at 500 MHz.