Title :
A fast-locking PLL architecture for efficient cycling of power-saving states in mobile electronic devices
Author :
August, Nathaniel J. ; Rifani, Michael C.
Abstract :
Extended battery operation and quick wake-up time are important features in mobile consumer electronic devices. When a PLL generates the system clock, acquisition time can consume a significant portion of a sleep cycle, wasting energy that could provide useful processing. This paper presents a PLL architecture that improves lock time by at least an order of magnitude compared to an existing PLL.
Keywords :
consumer electronics; mobile handsets; phase locked loops; extended battery; fast-locking PLL architecture; mobile consumer electronic devices; phase locked loops; power-saving; Batteries; Clocks; Consumer electronics; Feedback; Frequency measurement; Internet; Phase locked loops; Sleep; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Consumer Electronics, 2009. ICCE '09. Digest of Technical Papers International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-4701-5
Electronic_ISBN :
978-1-4244-2559-4
DOI :
10.1109/ICCE.2009.5012163
