Analysis of implementation opportunities for selected conventional counter-based circuits in selected FPGA structures in terms of time performance

Among many parameters that are crucial for performance of FPGA (Field Programmable Gate Arrays) structures the high operation speed combined with reasonable and cost-efficient layout seems to be the most important feature. In pace with evolution of FPGA structures a common belief has spread out that each subsequent FPGA structure, originated from the same family, is better than its predecessor in terms of quality, efficiency and operation speed of circuits implemented within such a structure. However, authors of this study, being forced to simultaneously use both less and more recent structures have come to the conclusion that such a belief is not obvious and need not be true under all circumstances. It is why they decided to verify their expectations on the basis of experiments associated with implementation of a certain digital circuit family, preferably very popular and in common use. Thus, the experiments were focused on conventional counter structures, both synchronous and asynchronous, that were implemented within the FPGA structures from XILINX. This study is intended to demonstrate that employment of the most recent FPGA structures for implementation of typical digital circuits (in particular counters and the like) is not always the most beneficial solution leading to the desired effects. It is recommended to compare the final outcome from implementation of the same circuit in FPGA structures from various families, including less recent ones that may prove more beneficial, not only by virtue of the logic structure but also the commercial properties.