A BIST PLA design for high fault coverage and testing by an interleavingly crosspoint counting

A built-in-self testable (BIST) programmable logic array (PLA) is designed where an interleaving counting technique of crosspoint (cp) devices on the product lines has been used. The proposed technique reduces the test application time by a substantial amount. To implement this idea, the product lines are re-arranged according to the number of cp devices. After re-arranging, if two consecutive product lines differ by more than one cp device then a single product line is added in between these two lines in contrast to multiple ones. The test pattern generator and response evaluator circuits are simple and consist of mainly shift registers and counters which reduce the delay per test as opposed to conventional parity checkers. The proposed technique has extremely high fault coverage. All the single faults and most of the multiple faults are covered. Even in the worst case, the fault coverage is close to 100%