Minimising Dynamic Power Consumption in On-Chip Networks

The provision of a general-purpose on-chip communication network is becoming increasingly important in the design of complex SoCs and chip-multiprocessors. In this paper we explore how the power consumed by such on-chip networks may be reduced through the application of clock and signal gating optimisations. We describe how the effectiveness of such optimisations may be maximised and demonstrate that very large reductions in power requirements are possible. A detailed analysis of where power is consumed in an optimised on-chip network is then provided. Results are obtained from fully place and routed standard-cell designs implemented in a 90nm technology. Our 64-bit on-chip network has a maximum operating frequency of 800MHz, in the best-case the combined latency for traversing a network router and link is a single clock cycle