MBIST design and implementation of a H.264/AVC video decoder chip

Author

Hou, Ligang ; Wu, Wuchen ; Zhu, Jiahui

Author_Institution

VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China

Volume

1

fYear

2010

Abstract

This paper implemented MBIST in a H.264/AVC video decoder chip, Neptune. Neptune has 1.5 million gates, 37 memory blocks. In need of testing, a complete design for test should be done. This paper mainly designed and implemented Memory BIST targeting the 34 RAM block, except the 3 ROM blocks. The design included building design flow, choosing algorithm, generating background data and BIST controller integration. By BIST controller reuse, circuit area was saved. Working mode simulation, test time analysis, fault coverage analysis, circuit performance evaluation were done. The result showed that the MBIST achieved 100% fault coverage by a 2.49% increase in chip area.

Keywords

built-in self test; video coding; BIST controller integration; H.264/AVC video decoder chip; MBIST design; memory block; test time analysis; working mode simulation; Algorithm design and analysis; Automatic voltage control; Built-in self-test; Circuit faults; Random access memory; Signal processing algorithms; BIST; H.264/AVC; fault coverage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems (ICSPS), 2010 2nd International Conference on

Conference_Location

Dalian

Print_ISBN

978-1-4244-6892-8

Electronic_ISBN

978-1-4244-6893-5

Type

conf

DOI

10.1109/ICSPS.2010.5555519

Filename

5555519