Title :
LATCHSIM-a latch-up simulator in VLSI CAD environment for CMOS and BiCMOS circuits
Author :
Bandyopadhyay, A. ; Verma, P.R. ; Bhattacharyya, A.B. ; Zarabi, M.J.
Author_Institution :
Semicond. Complex Ltd., Nagar, India
Abstract :
This paper presents a generalised latch-up simulator LATCHSIM for the design optimization of latch-up free layout configuration in CMOS and BiCMOS VLSI circuits. The core of the algorithm used in LATCHSIM is based on the fundamental principle of charge neutrality and is solved through a graphical approach to predict the entire latch-up trace for any given layout configuration under different operational and environmental conditions. LATCHSIM has been interfaced appropriately with the popular process simulator SUPREM to determine the effect of process variation on latch-up. The paper presents initial lest results of LATCHSIM validated for SCL´s 1.2 μm salicided double metal CMOS technology
Keywords :
BiCMOS integrated circuits; VLSI; circuit layout CAD; digital simulation; electrical faults; semiconductor device models; semiconductor process modelling; 1.2 micron; BiCMOS circuits; CMOS circuits; LATCHSIM; SUPREM; VLSI CAD environment; VLSI circuits; charge neutrality; design optimization; latch-up simulator; latchup free layout configuration; process simulator; salicided double metal CMOS technology; BiCMOS integrated circuits; Character generation; Circuit simulation; Current-voltage characteristics; Design automation; Layout; Leakage current; Predictive models; Very large scale integration; Voltage;
Conference_Titel :
VLSI Design, 1994., Proceedings of the Seventh International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-8186-4990-9
DOI :
10.1109/ICVD.1994.282715
