Instruction scheduling for the Motorola 88110

Author

Smotherman, Mark ; Chawla, Shuchi ; Cox, Stan ; Malloy, Brian

Author_Institution

Dept. of Comput. Sci., Clemson Univ., SC, USA

fYear

1993

Firstpage

257

Lastpage

262

Abstract

The Motorola 88110 is an advanced superscalar design. The processor can issue up to two instructions per cycle among ten functional units, and it includes sophisticated load-store, speculative execution, exception recovery, and branch target buffer facilities. This paper examines several computationally inexpensive instruction scheduling strategies for a post-processor code optimizer for the 88110, including basic block scheduling using reservation tables for writeback buses as well as functional units, delayed branch removal, loop alignment, and special loop entry scheduling. For a set of 32 loop-intensive benchmarks, a combination of delayed branch removal and loop alignment yields the best code improvement

Keywords

microprocessor chips; reduced instruction set computing; Motorola 88110; RISC; branch target buffer; delayed branch removal; exception recovery; instruction scheduling; loop alignment; reservation tables; superscalar design; Buffer storage; Computer aided instruction; Computer science; Databases; Decoding; Delay; Performance gain; Processor scheduling; Reduced instruction set computing; Springs;

fLanguage

English

Publisher

ieee

Conference_Titel

Microarchitecture, 1993., Proceedings of the 26th Annual International Symposium on

Conference_Location

Austin, TX

Print_ISBN

0-8186-5280-2

Type

conf

DOI

10.1109/MICRO.1993.282737

Filename

282737